TopMyGrade

GCSE/Computer Science/OCR

1.1.1The CPU — purpose, the fetch–decode–execute cycle, common CPU components (ALU, CU, cache, registers)

Notes

The CPU: fetch–decode–execute cycle and components

The CPU (Central Processing Unit) is the brain of the computer. OCR J277 Paper 1 regularly sets 4–6 mark questions on the CPU — both short-answer component identification and explain-the-cycle questions.

Components of the CPU

ComponentFunction
ALU (Arithmetic Logic Unit)Performs arithmetic operations (+, −, ×, ÷) and logical/comparison operations (AND, OR, NOT, >, <, =)
CU (Control Unit)Manages and coordinates all CPU operations; sends control signals; manages the fetch–decode–execute cycle
CacheVery fast, small memory built into the CPU; stores frequently used instructions/data so the CPU doesn't wait for RAM
Registers (general)Very fast temporary storage locations inside the CPU

Key registers

RegisterFull nameFunction
PCProgram CounterHolds the memory address of the next instruction to be fetched
MARMemory Address RegisterHolds the address currently being read from or written to
MDRMemory Data RegisterTemporarily holds the data being transferred to/from memory
ACCAccumulatorHolds the result of ALU calculations
CIRCurrent Instruction RegisterHolds the instruction currently being decoded/executed

The fetch–decode–execute (FDE) cycle

The CPU works by repeating three steps millions of times per second:

1. FETCH

  • Contents of PC copied to MAR.
  • Instruction at the address in MAR is fetched from RAM and copied to MDR.
  • Contents of MDR copied to CIR.
  • PC is incremented (increased by 1) to point to the next instruction.

2. DECODE

  • CU decodes the instruction in CIR.
  • CU determines what operation is needed and what data is involved.

3. EXECUTE

  • CU sends control signals to relevant components.
  • If arithmetic/logic: ALU performs the operation; result stored in ACC.
  • If memory access: data moved to/from RAM via MAR/MDR.
  • If a branch/jump: PC updated to the new address (not just incremented).

Common OCR exam mistakes

  1. Saying the PC holds the current instruction — it holds the address of the next instruction. The CIR holds the current instruction.
  2. Forgetting to mention that PC is incremented after the fetch — this is a frequently tested step.
  3. Saying the ALU does all processing — the CU coordinates everything; only arithmetic and logic go to the ALU.
  4. Confusing cache with RAM — cache is smaller, faster, and inside/close to the CPU.

AI-generated · claude-opus-4-7 · v3-ocr-computer-science

Practice questions

Try each before peeking at the worked solution.

  1. Question 16 marks

    Describe the fetch–decode–execute cycle

    Describe the stages of the fetch–decode–execute cycle. [6 marks]

    Ask AI about this

    AI-generated · claude-opus-4-7 · v3-ocr-computer-science

  2. Question 24 marks

    CPU components

    Give the function of each of the following CPU components:
    (a) ALU [1]
    (b) CU [1]
    (c) Cache [1]
    (d) Program Counter (PC) [1]

    Ask AI about this

    AI-generated · claude-opus-4-7 · v3-ocr-computer-science

  3. Question 33 marks

    Register identification

    Which register holds:
    (a) The instruction currently being decoded? [1]
    (b) The result of an ALU calculation? [1]
    (c) The memory address currently being accessed? [1]

    Ask AI about this

    AI-generated · claude-opus-4-7 · v3-ocr-computer-science

  4. Question 42 marks

    Von Neumann vs Harvard architecture

    State one difference between Von Neumann architecture and Harvard architecture. [2 marks]

    Ask AI about this

    AI-generated · claude-opus-4-7 · v3-ocr-computer-science

Flashcards

1.1.1 — The CPU — purpose, the fetch–decode–execute cycle, common CPU components (ALU, CU, cache, registers)

10-card SR deck for OCR Computer Science (J277) topic 1.1.1

10 cards · spaced repetition (SM-2)